LabVIEW 8.5 FPGA Module Win32Eng LabVIEW8.5FPGA模块LVFPGA85英文版
LabVIEW 8.5 FPGA Module Win32Eng LabVIEW8.5FPGA模块LVFPGA85英文版NI LabVIEW FPGA模块可帮助您开发和调试自定义硬件逻辑，并部署到NI FPGA硬件上。
LabVIEW FPGA是LabVIEW的一个软件附件，您可以通过高度集成的开发环境、IP库、高保真模拟器和调试功能，更高效地设计基于FPGA的系统。您可以创建FPGA VI，将I/O直接访问与用户定义的LabVIEW逻辑相结合，为数字协议通信、硬件在环仿真和快速控制原型等应用定义自定义硬件。虽然LabVIEW FPGA模块包含许多内置信号处理程序，但您也可以集成现有的硬件描述语言（HDL）代码以及第三方IP。
FPGA从2018版开始，提供64位版本和32位版本。而之前的则只有32位版本。64位版本的，仅有英文版。而32位版本的，则通常会有英文版、日文版、中文版等。本论坛大部分的日文版不提供下载（有少数几个没有找到中文版的有提供日文版）。部分年代版本的，则没有中文版的资源，请使用英文版。
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NI LabVIEW 8.5 FPGA Module
文件名: NI LabVIEW 8.5 FPGA Module CD1.zip
文件大小: 453953849 字节 (432.92 MB)
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文件名: NI LabVIEW 8.5 FPGA Module CD2.zip
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NI LabVIEW 8.5 FPGA Module ReadmeAugust 2007ni.com/supportThis file contains important last-minute information about the LabVIEW 8.5 FPGA Module.Supported PlatformsThe LabVIEW 8.5 FPGA Module supports the following platforms:
[*]Windows 2000 Professional (Service Packs 2, 3, and 4)
[*]Windows XP Professional (Service Packs 1 and 2)
[*]Windows Vista Business. However, the Xilinx tools do not officially support Windows Vista. National Instruments obtained permission from Xilinx to allow LabVIEW FPGA Module customers to use the tools on Windows Vista, with the disclaimer that Xilinx will not be able to fix any bugs found that are specific to the Windows Vista OS. National Instruments tested the Xilinx tools, as they are used by the LabVIEW FPGA Module, and did not find any issues related to Windows Vista. If you encounter problems with the Xilinx tools specific to Windows Vista, you might be required to compile using Windows XP or Windows 2000. National Instruments will not be liable for any problems or issues related to the use of Xilinx tools with Windows Vista.
InstallationYou must install LabVIEW 8.5 before you install the FPGA Module 8.5. Refer to the LabVIEW FPGA Module Release and Upgrade Notes for more information about installation instructions. The LabVIEW FPGA Module Release and Upgrade Notes is included as a booklet with the kit. You also can access this document directly from the installation CD or after installation by selecting Help»Search the LabVIEW Help in LabVIEW and navigating to the FPGA Module»FPGA Module Related Documentation topic on the Contents tab.Known IssuesThe following sections describe known issues at the time of the FPGA Module 8.5 release. Refer to the Knowledge Base at ni.com for the most recent information about known issues.Installation Issues
Issues with Importing FPGA Module 1.x Files
General Issues
Host VI Issues
Documentation IssuesInstallation Issues
[*]TCP must be installed—Most Windows installations have TCP installed. The LabVIEW FPGA Module communicates with the LabVIEW FPGA Compile Server through TCP. If TCP is not installed, LabVIEW returns the Error Contacting Server message when it attempts to contact the LabVIEW FPGA Compile Server. Refer to the Knowledge Base for more information about manually installing TCP support.
[*]Slow installation/uninstallation progress—If you click the Modify button in the National Instruments Software dialog box, available in the Add or Remove Programs utility, after you install the LabVIEW FPGA Module, the installer can take up to 10 minutes to initialize without any change in the progress indicator bar.
[*]Incorrect mutation—You must install LabVIEW 8.5 and then the FPGA Module 8.5 before you mass compile existing VIs. If you mass compile existing VIs before you install the FPGA Module 8.5, the following VIs might have mutation issues: Sine Wave Generator, Discrete Delay, Quantizer, Saturation Add, Saturation Subtract, Saturation Multiply, Look-Up Table 1D, Analog Period Measurement, Butterworth Filter, FIFO Read, FIFO Write, HDL Interface Node, Open FPGA VI Reference, Read/Write Control, Call VI, Close FPGA VI Reference, Invoke Method, Up Cast, FPGA I/O Method Node, and FPGA I/O Property Node.
Issues with Importing FPGA Module 1.x Files
[*]Import utility changes the size of FPGA FIFOs that use block RAM—The import utility causes the FPGA FIFOs using block memory to change size. Right-click the FPGA FIFO in the Project Explorer window and select Properties from the shortcut menu to view the newly configured depth of the FIFO.
[*]Imported host VI broken—The host VI might import improperly to LabVIEW 8.5 if any of the following conditions apply: you use constants for the HW Exec Ref parameter on the block diagram, you use Call By Reference Nodes that pass the HW Exec Ref parameter, or you use strict type definitions of the HW Exec Ref parameter with property nodes to get or set their value. Open the host VI and manually replace all instances of the HW Exec Ref that are broken with the new HW Exec Ref from the Open FPGA VI Reference function.
[*]Imported FPGA VI broken—The FPGA VI might import improperly to LabVIEW 8.5 if any of the following conditions apply: you have multiple aliases pointing to the same resource or you have aliases with the same name that point to different resources. Edit the resources in the Project Explorer window.
[*]Importing FPGA Module 1.0 VIs broken due to missing flag for Autopreallocate arrays and strings—An FPGA VI created with the FPGA Module 1.0 might be broken after importing the VI to LabVIEW 8.5. Make sure that a checkmark appears in the Autopreallocate arrays and strings checkbox. You can find the checkbox by navigating to the Execution category of the VI Properties dialog box for the FPGA VI.
[*]Import utility replaces Abort method with Reset method—A host VI created with the FPGA module 1.x might have used the Abort method with an Invoke Method function or as part of the Close FPGA VI Reference. The import utility replaces the Abort method with the Reset method. The Abort method in the FPGA Module 1.x reset the FPGA VI to default values. The Reset method in the FPGA Module 8.5 resets the FPGA VI to default values. In the FPGA Module 8.5, the Abort method stops the FPGA VI but does not reset the values to their default values. By replacing the Abort method with the Reset method, the import utility preserves behavior of your program. No action on your part is necessary.
General Issues
[*]Windows XP Service Pack 2 displays security alert when you launch the LabVIEW FPGA Compile Server—If you have Windows XP Service Pack 2 installed, a security alert dialog box appears when you launch the LabVIEW FPGA Compile Server for the first time. If you select the Keep blocking this program option, the LabVIEW FPGA Compile Server cannot accept incoming connections from a remote computer. Select Unblock this program, despite the security risk to configure your computer to launch the LabVIEW FPGA Compile Server without any changes in server functionality. Refer to the KnowledgeBase for more information about correcting this problem.
[*]FPGA FIFO reset behavior—When you use an FPGA target emulator, FPGA FIFOs reset when the VI is stopped and then started again. When you use an FPGA target with Interactive Front Panel Communication, FPGA FIFOs do not reset when the FPGA VI is stopped and then started again. To reset the FIFO, right-click the FPGA target in the Project Explorer window and select Download from the shortcut menu. When you control an FPGA VI using Programmatic FPGA Interface Communication, use the Close FPGA VI Reference function with the Close and Reset shortcut menu option selected or the Invoke Method with the Reset method selected to reset FPGA FIFOs.
[*]Multiplying fixed-point data might not meet 40 MHz timing—If you use the Multiply function with inputs above 32 bits that contain fixed-point data, the function might not meet 40 MHz timing requirements. You can place the Multiply function inside a single-cycle Timed Loop that is configured at a lower clock rate.
[*]Saving to LabVIEW 8.0—The FPGA Module 8.5 does not support saving to LabVIEW 8.0. You can save to LabVIEW 8.2 and then save to LabVIEW 8.0.
Host VI Issues
[*]Host VIs with VISA name controls—The Open FPGA VI Reference function no longer supports VISA name controls. When you open an existing host VI that uses a VISA name control, the FPGA Module includes a Concatenate Strings function on the block diagram to allow the VI to work with the Open FPGA VI Reference function, which requires an NI-RIO name control. You can remove the Concatenate Strings function if you change the VISA name control to an NI-RIO name control.
[*]Opening host VIs that include the FPGA Interface functions take several minutes to open—Host VIs that contain the FPGA Interface functions might take a long time to open because the FPGA Interface functions need several support files to manage the interface with FPGA VIs. The FPGA Interface functions also verify the status of the FPGA VI when you open the host VI.
[*]Disable legacy USB support on PXI Embedded Real-Time controllers—You must disable Legacy USB Support in the BIOS of PXI Embedded Real-Time controllers when you use the FPGA Interface functions. Specific controllers affected are the PXI-817x controllers and any other third-party systems that use the PhoenixBIOS. Failure to disable Legacy USB Support can result in the Open FPGA VI Reference function failing to download the FPGA VI without returning an error. Subsequent reads using the Read/Write Control function return values where all bits of the data type are set to 1 without an error. National Instruments also recommends disabling Legacy USB Support when you use the LabVIEW Real-Time Module to reduce jitter. Disable Legacy USB support by configuring the BIOS of the controller. Refer to the Configuring RT Target Settings topic in the LabVIEW Help for information about configuring the BIOS.
Documentation Issues
[*]Support for 64-bit Windows Vista—The LabVIEW FPGA Module Release and Upgrade Notes lists only the 32-bit version of Windows Vista as supported. However, the FPGA Module also supports the 64-bit version of Windows Vista.
[*]Default for host part of FIFOs—The Transferring Data Between the FPGA and the Host VI topic in the LabVIEW Help states "If you do not specify the size of the host computer part of the FIFO in the host VI, the host computer part size defaults to twice the size of the FPGA part of the FIFO." However, the default is actually 10,000 elements.
Bug FixesThe following items are the IDs and titles of a subset of issues fixed in the FPGA Module 8.5.
Bug IDFixed Issue
478E06KQCode generation error from memory, FIFO, and FPGA I/O items if item name in Project Explorer window changes case while the VI is out of memory.
496932KQFPGA VI needs to be saved every time it is opened.
48GMNK8RFPGA case structure doesn't work when signed negative numbers or 64-bit numbers are connected to case selector.
47RCEBLJHost interface can't read an FPGA indicator that is a typedef in a library.
43J8K1LJInteractive mode does not update front panel control as expected.
3X8HQKLJCompile fails when HDL Interface Node references a .vhd file that has repetitious library.
3V57R3LJObjects with embedded shift registers should allow the user to set an initial value.
3KP5PPTPUnable to pass occurrence to subVI.
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